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IMEC creates first 5nm chip.
CalmOceans
Member UncommonPosts: 2,437
in Hardware
http://www.electronicsweekly.com/news/business/manufacturing/imec-and-cadence-tape-out-first-5nm-ic-2015-10/
LEUVEN, Belgium and SAN JOSE, Calif., October 7, 2015—Nano-electronics research center imec and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence® Innovus™ Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.
LEUVEN, Belgium and SAN JOSE, Calif., October 7, 2015—Nano-electronics research center imec and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence® Innovus™ Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.
